1. Field of the Invention
This invention relates to structures and methods of assembly of integrated circuit chips. More particularly, this invention relates to mounting discrete decoupling capacitors on the surface of IC chips.
2. Description of the Related Art
Current wirebonding packages, for example, ball grid arrays (BGA), suffer from power/ground noise due to the inductance of wirebonds and package leads. This issue becomes severe in advanced chips performing at high frequency and low voltage. Flip chip packages are now used to reduce the inductance from wirebonds. However, the industry infrastructure for flip chip packages is not so mature as wirebonding packaging. Most importantly, flip chip packages require high density substrates which are much more expensive than wirebonding substrates. Wirebonds act as the fan-out metal lines; therefore the routing density on substrates is relaxed. Other approaches attempt to solve the power/ground problem by building on-chip decoupling capacitors using thin-film IC processes for the wirebonding packages. However, the built-in capacitors cannot provide large enough magnitude capacitance for decoupling purposes.
U.S. Pat. Nos. 6,303,423 and 6,515,369, both by M. S. Lin, teach methods and structures of mounting a discrete component on the surface of an IC chip. Related patent application Ser. No. 10/855,086 discloses methods of making both solder bumps and wirebond pads on the same wafer. U.S. Pat. Nos. 6,495,442 and 6,383,916 to M. S. Lin et al disclose a post-passivation interconnection process. U.S. Pat. Nos. 6,184,574 and 6,504,236 both to Bissey disclose an integrated circuit lead frame with capacitors formed on the lead frame and bonded to the bottom surface of the chip for decoupling purposes.